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1 of 25 april 9, 2001 ? 2000 integrated device technology, inc. dsc 5602 features features features features rc32300-family system controller ? direct connection between rc32364 and rc32134 ? up to 75 mhz operation ? drives latched address bus to memory and peripherals ? direct control of optional external data buffers ? programmable system watch-dog timers ? big or little endian support interrupt control ? provides services for internal and external sources ? allows status of each interrupt to be read and masked three general purpose 32-bit timer/counters programmable io (pio) ? input/output/interrupt source ? individually programmable sdram/edodram controller (32-bit memory only) ? 4 banks, non-interleaved, 256 mb total ? automatic refresh generation uart interface ? two 16550 compatible uarts ? baud rate support up to 1.5m 8/16/32-bit boot prom support boundary scan jtag interface (ieee std. 1149.1 compatible) memory & peripheral controller ? 6 banks, up to 8mb per bank ? 8/16/ or 32-bit interface per bank ? supports flash rom, sram, dual-port memory, and periph- eral devices ? intel or motorola style io supports external wait-state genera- tion 4 dma channels ? 4 general purpose dma, each with endianness swappers and byte lane data alignment ? any channel can be used for pci ? supports memory-to-memory, memory-to-i/o,memory-to- pci, pci-to-pci, i/o-to-i/o transfers, and i/o support of scatter/gather ? supports chaining via linked lists of records ? supports unaligned transfers ? supports burst transfers ? programmable burst size pci bridge ? 32-bit pci, up to 33 mhz ? revision 2.1 compliant ? target and master ? host or satellite ? three slot pci arbiter, on-chip ? serial eeprom support, for loading configuration registers 3.3v core operation 3.3v i/o operation with 5v tolerant i/o 208 pin pqfp package block diagram block diagram block diagram block diagram the idt logo is a registered trademark. rc64145, rc64474, rc64475, rc32134, rc4600, rc4640, rc4650, rc4700, rc3041, rc3051, rc3 052, rc3081, riscontroller, and riscore are trademarks of inte- grated device technology, inc. timer, uart, interrupt modules cpu i/f dma channels edo/sdram control memory i/o control rc32134 pci bus pci i/f and bridge data & address bus sdram/edodram control memory & i/o control IDT79RC32134 riscore32300 tm family system controller chip
2 of 25 april 9, 2001 IDT79RC32134 description description description description the IDT79RC32134 is a high performance system controller chip that supports idt?s riscore32300 cpu family. the rc32134 offers a direct connection to idt?s rc32364 32-bit embedded microprocessor. the rc32134 provides the system logic for boot memory, main memory, i/o, and pci. it also includes on-chip peripherals such as dma chan- nels, reset circuitry, interrupts, timers, and uarts. together, the rc32364 cpu and the rc32134 system controller form a complete cpu subsystem for embedded designs. figure 1 illustrates the typical system implementation, based on the rc32364 cpu and the rc32134 system controller. the rc32134 inter- faces directly to the rc32364 and provides all of the necessary control and address signals to drive the external memory and i/o. note that, depending on the loading of the cpu data bus, external data buffers could be used to reduce the loading and isolate different memory regions. as illustrated in the system block diagram, the memory and i/o data path is external to the rc32134. device overview device overview device overview device overview the rc32134 interfaces directly to the rc32364?s system bus. the rc32134 latches the address from the rc32364 internally and decodes it to detect which memory, i/o, or on-chip peripheral is being accessed, per the internal address map of the rc32134. the rc32134 generates all necessary control signals and address buses to the external memory and i/o. for main memory, i/o, on-chip peripherals, registers, and pci, the rc32134 divides the physical address space into 14 different regions. the data path for the local memory and peripherals (with the excep- tion of pci) is external to the rc32134. the data path from the pci bus and from the internal peripherals and registers is internal to the rc32134. memory controller. the memory controller on the rc32134 provides all of the address buses and control signals for interfacing the rc32364 cpu to standard sram, prom, flash, and i/o and includes the boot prom interface. the memory controller provides six individual chip selects and supports 8,16, and 32-bit wide memory and i/ os. two chip selects have highly configurable memory address ranges, allowing selection of various memory types and widths to be supported. the rc32134 provides controls for optional external data transceivers for systems that require fast signalling with large loads. sdram controller. the sdram controller optimization provides higher throughput while using available dram technology. the sdram control register directly manages four banks of 32-bit physical non-inter- leaved memory. each bank is 32-bits wide and supports a maximum of 64 mb per bank. total memory support is 256 mb. the sdram controller has a built in refresh generator. edo dram controller. the rc32134 edo dram controller supports up to 4 banks of non-interleaved 32-bit wide edo drams. most of the edo dram pins are shared with the sdram controller, and as such, the two operations can not be simultaneously enabled. selec- tion between sdram or edo dram is made at boot-time through system software operations. the edo supports 256 mb total of edo dram. the edo controller has a built in refresh generator. pci interface. to transfer data between main memory and the pci bus, the rc32134 incorporates a pci interface. at reset time the pci interface can be configured as either a host or satellite interface. the pci interface supports 32-bit pci at up to 33mhz and is pci specifica- tion, revision 2.1 compliant. figure 1 system block diagram rc32364 clock 32-bit data bus rc32134 sdram cpu i/f dram ctl serial pio timers, uart, interrupt ctl dma channels memory & i/o ctl address & control memory & i/o pci bridge with arbiter 32-bit, 33mhz pci bus
3 of 25 april 9, 2001 IDT79RC32134 as a pci master, the rc32134 can generate memory, i/o, or config- uration cycles for direct local-to-pci bus accesses. the pci interface incorporates a 3-slot pci bus arbiter, which includes fixed and round robin arbitration modes. as a pci target, the rc32134 allows access to its internal registers and to the riscore32300 local bus through the pci i/o read and write, or memory read and write commands. the rc32134 pci interface supports swapping little endian data to big endian, when the cpu subsystem is configured as a big endian system. for more information on the pdci interface, please refer to the pci specification, revision 2.1. dma controller. four general purpose dma channels move data between source and destination ports. source and destination ports can be system memory, pci or i/o devices. any of the four channels can be used for pci initiator reads or writes. all four channels support a descriptor structure, to allow efficient data scatter/gather. the dma controller supports swapping of data between big and little endian memory and i/o subsystems by memory region. it also supports quad- word burst transfers. all external 16 and 8-bit memory i/os are treated as memory-mapped, word-aligned devices. expansion interrupt controller. the expansion interrupt controller provides the interrupt logic for software to analyze the various rc32134 generated system interrupts and adds to the control already provided through the cp0 registers of the rc32364. each system interrupt is registered and the pending status provided through this feature. the pending status can then be used to automatically generate a hardware interrupt to the cpu via individual mask bits. the pending interrupt status can also be optionally set or cleared by a direct software write. pio. programmable i/o (pio) pins are provided on the rc32134 so that any unused peripheral pins can be programmed for use as general purpose discrete i/o pins. these pio pins can be software programmed as bidirectional lines, allowing pin values to be software programmed in output mode and software readable while in the input mode. the pio pins can also be used as a source of interrupts to the cpu. maximum interfacing flexibility is thus provided without requiring extensive modifi- cations to the board. uart. the rc32134 incorporates two 16550 (an enhanced version of the 16450) compatible uarts. to relieve the cpu of software over- head, the 16550 uart can be put into fifo mode, allowing execution of either 16450 or 16550 compatible software. two sets of 16-byte fifos are enabled during the 16550 mode: one set in the receive data path and one set in the transmit data path. a baud rate generator is included that divides the system clock by 1 to 64k and provides a 16x clock for driving the transmitter and receiver logic. timers/counters. three on-chip 32-bit general purpose timers are provided on the rc32134. each timer consists of both a count and a compare register. the count register resets to zero and then counts upward until it equals the compare register. when the count and compare registers are equal, the tc_n output is asserted and the count is then reset to zero. jtag. board-level manufacturing debugging is facilitated through implementation of a fully compliant ieee std. 1149.1 jtag boundary scan interface. thermal considerations thermal considerations thermal considerations thermal considerations the rc32134 is guaranteed in a case temperature range of 0 c to +90 c, for commercial temperature devices; - 40 c to +90 c for indus- trial temperature devices. the speed (power) of the device and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. the equivalent allowable ambient temperature, t a , can be calculated using the thermal resistance from case to ambient ( ? ca ) of the given package. the following equation relates ambient and case temperatures: t a = t c - p * ? ca where p is the maximum power consumption at hot temperature, calculated by using the maximum i cc specification for the device. typical values for ? ca at various airflows are shown in table 1 revision history: revision history: revision history: revision history: july 21, 1999: changed the following: thermal resistance values; table 2, pin descriptions; logic diagram - rc32134; clock parameter temperature from 85 to 90 degrees; ac timing characteristics - rc32134; dc elec- trical characteristics; power consumption - rc32134; absolute maximum ratings diagram; pin-out 208-pqfp table; rc32134 alternate signal functions. september 2, 1999: corrected package drawing from 144-pin to 208-pin. november 1, 1999 : removed maximum column from power consumption table. november 9, 1999 : moved pin 208 (sdram_245_oe_n) from low drive to high drive in dc electrical characteristics table. april 28, 2000 : added mode configuration interface reset sequence figure on page 14. ? ca airflow (ft/min) 0 200 400 600 800 1000 208 pqfp 18 14 11 9 8 7 table 1 thermal resistance ( ? ca) at various airflows
4 of 25 april 9, 2001 IDT79RC32134 january 6, 2000 : ?re ordered alternate signals for the pio interface in table 2 and changed pci_eeprom_mdi to pci_eeprom_mdo. ? switched alternate pin signals for pci_eeprom_mdo and pci_eeprom_mdi in pci interface section of table 2. ? switched alternate pin signals for uart_rx and uart_tx in uart interface section of table 2. ? in rc32134 alternate signal functions table, changed pin designations under alt #1 column for pins 22 - 29. ? changed 64145 references to 32134 in the note section of the ac timing characteristics table. ? updated the user manual timing diagram reference column in the ac timing characteristics table . march 20, 2000 : changed pci speed to 33 mhz. june 20, 2000 : values were revised for three local memory/periph- eral bus signals in the ac timing characteristics table. july 12, 2000 : revised tsu and thld symbol numbers in uart section of ac timing characteristics table and revised reference to timing diagram. april 9, 2001 : in the local memory/peripheral bus section of the ac timing characteristics table, deleted cpu_coldreset_n associated with tsu4.
5 of 25 april 9, 2001 IDT79RC32134 pin description table pin description table pin description table pin description table the following table lists the pins provided on the rc32134. note that several pins are multiplexed and have been assigned alter nate functions. these pins are designated and defined accordingly throughout this table. also note that those pin names followed by _n are acti ve-low signals. pin name type alternate signal(s) description local memory and peripheral pins cpu_ad[31:0] i/o not applicable cpu address/data bus this is the rc32134?s primary multiplexed and bidirectional address and data bus. the rc32134 latches this bus internally and uses it to generate the necessary address lines to the external memory and peripherals. if the transaction is a write, the cpu then drives data on cpu_ad(31:0). during cpu generated transactions, the cpu drives address(31:4) into the cpu_ad bus, during its address phase. during dma generated transactions (or rc32134 internal register reads), the address phase is unused and the chip drives data during a write. cpu_addr[3:2] i not applicable cpu lsb address bus during cpu generated transactions, the cpu drives address(3:2) onto the cpu_addr bus. the rc32134 does not internally use the cpu_addr bus during the data phase. however, 8- or 16-bit memory or i/o systems must attach these two pins instead of mem_addr(3:2). cpu_ale i not applicable cpu address latch enable during cpu generated transactions, this signal indicates that the cpu_ad (31:0) is driving a valid address and can be latched internally by the rc32134. cpu_cip_n i not applicable cpu cycle in progress during cpu generated transactions, this active-low signal indicates that a bus transaction is active. an external pullup resistor is required. cpu_wr_n i not applicable cpu write status during cpu generated transactions, this active-low signal indicates whether or not a write is occur- ring. if a write is not occurring, then the implication is that a read is in progress. cpu_be_n[3:0] i not applicable cpu byte enable bus during cpu generated transactions, these active-low signals indicate which byte lanes are in use. note: the table below indicates which cpu_be_n signal corresponds to which byte lane, whether or not the system is in big or little endian mode cpu_ack_n o not applicable cpu acknowledge during cpu generated transactions, this active-low signal is generated by the rc32134 to indicate that the present data have been accepted. cpu_last_n i not applicable cpu last data during cpu generated transactions, this active-low signal indicates during the data phase that the present data is the last data. cpu_buserr_n o not applicable cpu bus error during both cpu and dma generated transactions, this active-low signal indicates that a bus error has occurred. this signal can also be optionally attached to an interrupt line. table 2 rc32134 pin descriptions (page 1 of 8) data bits cpu_be_n[0] 7:0 cpu_be_n[1] 15:8 cpu_be_n[2] 23:16 cpu_be_n[3] 31:24
6 of 25 april 9, 2001 IDT79RC32134 cpu_masterclk i sdram_clk cpu master system clock provides the basic system clock. this clock must be the same clock that is provided to the rc32364 and also, if used, to sdram. cpu_coldreset_n i not applicable cpu cold reset this active-low signal is asserted to the rc32364 cpu and rc32134 after v cc becomes valid on the initial power-up. the reset initialization vectors, for both the rc32364 and the rc32134, are latched by cold reset. cpu_reset_n o not applicable cpu warm reset this active-low signal is a secondary reset signal asserted to the cpu at least 256 clocks after cold reset, allowing, for instance, stabilization of rc32364?s pll. cpu_busreq_n o not applicable cpu bus request this active-low signal requests the cpu bus from the rc32364, for instance, by rc32134 to perform a dma operation. cpu_busgnt_n i not applicable cpu bus grant this active-low signal is a cpu bus grant from the rc32364, indicating that the local cpu bus has been released to the rc32134. cpu_int_n o interrupt_n cpu interrupt this active-low signal is an interrupt indication to the cpu from rc32134?s interrupt controller. note: this pin is typically hooked up to the cpu?s interrupt 3. cpu_dt_r_n o mem_245_dt_r_n, sdram_245_dt_r_n, edodram_245_dt_r_n cpu direction transmit/receive this active-low signal controls the dt/r pin of an optional fct245 transceiver bank. it is asserted during dma read operations. this signal is tri-stated during cpu accesses (when the cpu owns the bus) and driven during dma generated accesses. note: an external pull-up resistor is required. pci interface pci_ad[31:0] i/o not applicable pci multiplexed address/data bus this address is driven by the bus master during initial frame_n assertion. the data is then driven by the bus master during writes; or the data is driven by the bus slave during reads. pci_cbe_n[3:0] i/o not applicable pci multiplexed command/byte enable bus the command bus (active high) is driven by the bus master during the initial frame_n assertion. the byte enable bus (active low) is driven by the bus master during the data phase(s). note: the table below indicates which cpu_be_n signal corresponds to which byte lane, whether or not the system is in big or little endian mode. pci_par i/o not applicable pci parity this signal indicates even parity of the pci_ad[31:0] bus and is driven by the bus master during address and write data phases. during the read data phase, this signal is driven by the bus slave. pci_frame_n i/o not applicable pci frame negated this active-low signal is driven by the bus master and indicates the duration of a pci transfer. asser- tion indicates the beginning of a bus transaction. de-assertion indicates the last data. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 2 of 8) data bits pci_be[0] 7:0 pci_be[1] 15:8 pci_be[2] 23:16 pci_be[3] 31:24
7 of 25 april 9, 2001 IDT79RC32134 pci_trdy_n i/o not applicable pci target ready negated this active-low signal is driven by the bus slave and indicates that the current data can complete (the bus slave can accept/drive data). pci_irdy_n i/o not applicable pci initiator ready negated driven by the bus master, this active-low signal indicates that the current data can complete (pci ini- tiator is ready to accept/drive data). pci_stop_n i/o not applicable pci stop negated driven by the bus slave this active-low signal terminates the current bus transaction. pci_idsel i pci_req_n[2] pci initialization device select host mode : pci_req_n[2] is an input indicating a request from an external device. satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. pci_perr_n i/o not applicable pci parity error negated driven by the receiving bus agent 2 clocks after the data is received, if a parity error occurs. pci_serr_n i/o not applicable system error driven by any agent, this active-low signal indicates an address parity error, data parity during a spe- cial cycle command, or any other system error. an external 2.7k (5v) ohm or 8.2k (3.3v) ohm pull- up resistor is required, per the pci revision 2.1 specifications. pci_clk i not applicable pci clock clock for pci bus transactions that uses the rising edge for all timing references. note that the pci clock does not need to be synchronized to the cpu_masterclk. pci_rst_n i not applicable pci reset negated in host mode, this active-low signal resets all pci related logic. in satellite mode, with boot from pci mode, this signal resets all pci related logic and also asserts the warm reset, cpu_rst_n, to the rc32134. and the rc32364. pci_devsel_n i/o not applicable pci device select negated this active-low signal is driven by the target to indicate that the target has decoded the present address as a target address. pci_req_n[2] i pci_idsel pci bus request #2 negated this is an active-low signal that in host mode is an input indicating a request from an external device. in satellite mode pci_req_n[2] is used as the pci_idsel pin, which selects this device during a configuration read or write. pci_req_n[1] i not applicable pci bus request #1 negated in host mode, pci_req_n[1] is an input indicating a request from an external device. in satellite mode pci_req_n[1] is unused. pci_req_n[0] i/o not applicable pci bus request #0 negated in host mode, this active-low signal is an input indicating a request from an external device. in satel- lite mode, pci_req_n[0] is an output indicating a request from this device. pci_gnt_n[2] o pci_inta_n pci bus grant #2 negated in host mode, this active-low signal is an output indicating a grant to an external device. in satellite mode, pci_gnt_n[2] is used as the pci_inta_n output pin. an external 5k ohm pull-up resistor is required, per the pci revision 2.1 specifications. note : in host mode, int_n[1] on the rc32364 can be used for a pci_inta_n input and pci_int[d:c:b]_n uses int_n[5:4:2] on the rc32364 bus interface. pci_gnt_n[1] o pci_eeprom_cs pci bus grant #1 negated in host mode, this active-low signal is an output indicating grants to external devices. in satellite mode, pci_gnt_n[1] is used as the pci_eeprom_cs output pin for serial chip select, for loading pci configuration registers in the rc32134 reset initialization vector pci boot mode. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 3 of 8)
8 of 25 april 9, 2001 IDT79RC32134 pci_gnt_n[0] i/o not applicable pci bus grant #0 negated in host mode, this active-low signal is an output indicating a grant to an external device. in satellite mode, pci_gnt_n[0] is an input indicating a grant to this device. pci_inta_n i/o pci_gnt_n[2] pci interrupt #a negated in host mode, pci_gnt_n[2] is an output indicating a grant to an external device. in satellite mode, pci_gnt_n[2] is used as the pci_inta_n output pin. an external pull-up is required, per the pci revision 2.1 specifications. note: in host mode, int_n[1] on the rc32364 can be used for a pci_inta_n input and pci_int[d:c:b]_n uses int_n[5:4:2] on the rc32364 bus interface. pci_lock_n i not applicable pci lock negated this active-low signal is driven by the bus master and indicates that an exclusive operation is occur- ring. pci_eeprom_mdo i/o pio[11] pci eeprom master data out in serial mode, this signal is an output pin from rc32134 that connects as an input to a serial chip for the serial data input stream. in pci satellite mode, it is an output pin from rc32134 that con- nects as an input to a serial chip for the serial data input stream for loading pci configuration reg- isters in the rc32134 reset initialization vector pci boot mode. this pin is also multiplexed as a pio pin. pci_eeprom_mdi i/o pio[8] pci eeprom master data in the serial mode provides an input pin to rc32134 from the output of a serial chip for the serial data output stream. the pci satellite mode provides an input pin to rc32134 from the output of a serial chip for the serial data output stream, for pci configuration registers in the rc32134 reset initialization vector pci boot mode. this pin is also multiplexed as a pio pin. pci_eeprom_cs i/o pci_gnt_n[1] pci eeprom chip select host mode: pci_gnt_n[1] is an output indicating grants to external devices. satellite mode: used as pci_eeprom_cs output pin for spi chip select for loading pci configuration registers in the rc32134 reset initialization vector pci boot mode. pci_eeprom_sk i/o pio[10] pci eeprom serial clock serial mode: output pin for serial clock. pci satellite mode: output pin for serial clock for loading pci configuration registers in the rc32134 reset initialization vector pci boot mode. this pin is also multiplexed as a pio pin. memory/i/o controller mem_addr[22:2] i/o edodram_addr[15:2] sdram_addr[15:13] sdram_addr[11:2] memory address bus these signals provide the memory or dram address, during a memory or dram bus transactiion. during each word data, the address increments either in linear or sub-block ordering, depending on the transaction type. for 32-bit system, use mem_addr[3:2] for the least significant address bits [3:2]. for 8 or 16-bit wide ports, to provide the least significant address bits [3:0], use cpu_addr[3:2] and cpu_be_n[1:0]. mem_cs_n[5:0] o not applicable memory chip select negated this active-low signal indicates that a memory or i/o bank is actively selected. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 4 of 8) mem_addr subsets mem_addr[22:20] i/o reset_boot_mode[1:0] reset_pci_host_mode mem_addr[15:2] i/o sdram_addr[15:13] sdram_addr[11:2] edodram_addr[15:2]
9 of 25 april 9, 2001 IDT79RC32134 mem_oe_n o not applicable memory output enable negated this active-low signal indicates that either a memory or i/o bank can output its data lines onto the cpu_ad bus. mem_we_n[3:0] o not applicable memory write enable negated bus these active-low signals indicate which bytes are to be written during a memory or i/o transaction. mem_wait_n i edo_dram_wait_n memory wait negated in mem, ioi, iom modes this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. in dpm (dual-port) mode , this signal allows dual-port busy signal to restart memory transaction. mem_245_oe_n o not applicable memory fct245 output enable negated this active-low signal controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n o cpu_dt_r_n memory fct245 direction xmit/rcv negated uses the cpu_dt_r_n pin. edodram controller edodram_addr[15:2] o mem_addr[15:2] edodram_addr/sdram_addr mode these are output signals that provide a dram address during a dram transaction. the dram address multiplexes between row and column addresses. during each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. allows an external memory debug emulator to inject wait-states. for more detail, see the user?s man- ual. edodram_ras_n[3:0] o sdram_cs_n[3:0] dram row address strobe negated bus sdram mode: provides chip select to each sdram bank. edodram mode: used as edodram_ras_n[3:0] pins to provide a ras signal for each edodram bank. edodram_cas_n[3:0] o sdram_bemask_n[3:0] dram column address strobe negated bus in the edodram mode these signals are used as edodram_cas_n[3:0] to provide a cas signal for each byte lane. in the sdram mode, these signals provide byte enables for each byte lane of all dram banks. edodram_oe_n o sdram_ras_n, sdram_245_oe_n dram edo output enable negated in the edodram mode , this active-low signal provides an output enable signal for reads for particu- lar oe types of edodram. this signal also controls the output enable to an optional fct245 trans- ceiver bank by asserting during both reads and writes to any dram bank. this signal also controls the output enable to each edo dram chip. alternatively, because the edodram controller always uses early writes and cas controlled non-interleaved reads, the oe_n pin, on each edo dram chip, can simply be tied to ground. the sdram ras mode is a control signal to all sdram banks. in sdram mode , this signal controls the output enable to an optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. edodram_we_n o sdram_we_n dram edo write enable negated in edodram mode, this active-low signal is used as the edodram_we_n pin to provide a write enable signal for edodram. write enable is valid at all times and high during refresh. in sdram mode, this signal provides the sdram we control signal to all sdram banks. edodram_wait_n i mem_wait_n dram wait negated in the edo dram mode , this active-low signal allows external wait-states to be injected at any time during the edo dram cycle. in the mem, ioi, iom modes , this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. the dpm (dual-port) mode allows the dual-port busy signal to restart memory transactions. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 5 of 8)
10 of 25 april 9, 2001 IDT79RC32134 edodram_245_oe_n o sdram_245_oe_n dram fct245 output enable negated in the sdram mode this active-low signal controls the output enable to an optional fct245 trans- ceiver bank by asserting during both reads and writes to any dram bank. in the edodram mode this signal controls the output enable to an optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. this signal also controls the output enable to each edo dram chip. alternatively, because the edodram controller always uses early writes and cas con- trolled non-interleaved reads, the oe_n pin, on each edo dram chip, can simply be tied to ground. edodram_245_dt_r_n o cpu_dt_r_n dram/mem fct245 direct xmit/rcv negated this active-low signal controls the dt/r pin of an optional fct245 transceiver bank. it is asserted during dma read operations. this signal is tri-stated during cpu accesses (when the cpu owns the bus) and drives during dma generated accesses. sdram controller interface sdram_addr[15:13] sdram_addr[11:2] o mem_addr[15:13] mem_addr[11:2] sdram address bus these signals are outputs providing a dram address during a dram transaction. the dram address multiplexes between row and column addresses. during each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. sdram_addr_12 o pio[9] sdram address line 12 this sdram address is dedicated to the sdram and multiplexes between the row address; and dur- ing the precharge command, the "all bank" indicator. sdram_ras_n o edodram_oe_n sdram ras negated sdram mode: provides sdram ras control signal to all sdram banks. edodram mode: provides an output enable signal for reads for particular oe types of edodram. sdram_cas_n o not applicable sdram cas negated this active-low signal provides an sdram cas control signal to all sdram banks. sdram_we_n o edodram_we_n sdram we negated sdram mode: provides sdram we control signal to all sdram banks. edodram mode: used as edodram_we_n pin to provide a write enable signal for edodram. write enable is valid at all times and high during refresh. sdram_clk i cpu_masterclk sdram clock this signal provides the basic system clock and must be the same clock that is provided to the rc32364 and also, if used, to sdram. sdram_cke o not applicable sdram clock enable in the sdram mode this signal provides the clock enable to all sdram banks. sdram_cs_n[3:0] o edodram_ras_n[3:0] sdram chip select negated bus in sdram mode, these active-low signals provide chip select to each sdram bank. in edodram mode they are used as the edodram_ras_n[3:0] pins and provide a ras signal for each edodram bank. sdram_bemask_n[3:0] o edodram_cas_n[3:0] sdram byte enable mask negated bus the sdram mode provides byte enables for each byte lane of all dram banks. to provide a cas signal for each byte lane, the edodram mode is used as edodram_cas_n[3:0]. sdram_245_oe_n o edodram_245_oe_n, edodram_oe_n sdram fct245 output enable negated in sdram mode, this active-low signal controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. in edodram mode this signal con- trols output enable to optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. also controls output enable to each edo dram chip. alternatively, because the edodram controller always uses early writes and cas controlled non-interleaved reads, the oe_n pin on each edo dram chip can simply be tied to ground. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 6 of 8)
11 of 25 april 9, 2001 IDT79RC32134 sdram_245_dt_r_n o cpu_dt_r_n sdram fct245 direction transmit/receive this active-low signal controls the dt/r pin of an optional fct245 transceiver bank and is asserted during dma read operations. this signal is tri-stated during cpu accesses (when the cpu owns the bus) and drives during dma generated accesses. dma interface dma_ready_n[1:0] i/o dma_done_n[1:0] pio[1:0] dma ready negated bus input pin for general purpose dma channels[1:0] that can initiate the next datum in the current dma descriptor frame. dma_ready_n[1:0] pins are not synchronized internally by the rc32134 and thus must meet the specified setup and hold time with respect to the input clock. dma_done_n[1:0] i/o dma_ready_n[1:0] dma done input pin for general purpose dma channels[1:0] that can terminate the current dma descriptor frame. interrupt controller interrupt_n i/o cpu_int_n interrupt negated uses cpu_int_n. this active-low signal is an interrupt indication to the cpu from rc32134?s interrupt controller. pio interface pio[11:0] i/o pci_eeprom_mdo pci_eeprom_sk sdram_addr_12 pci_eeprom_mdi uart _rx[0], uart_tx[0] uart_rx[1], uart_tx[1] timer_tc_n[0], timer_tc_n[1] dma_ready_n[0] dma_ready_n[1] programmable input/output general purpose pins that can each be configured as a general purpose input or general purpose output. the pci_eeprom_mdo, pci_eeprom_sk, and sdram_addr12 default to outputs. the rest default to inputs. timer/counter timer_tc_n[1:0] o timer_gate_n[1:0], pio[3:2] timer terminal count overflow negated output indicating that the timer has reached its count compare value and has overflowed back to 0. timer_gate_n[1:0] i timer_tc_n[1:0], pio[3:2] timer gate negated input indicating that the timer may count one tick on the next clock edge. uart interface uart_rx[1:0] i/o pio[7] pio[5] uart receive data bus uart mode: each uart channel receives data on their respective input pin. uart_tx[1:0] i/o pio[6] pio[4] uart transmit data bus uart mode: each uart channel sends data on their respective output pin. note that these pins default to inputs at reset time and must be programmed via the pio interface before being used as uart outputs. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 7 of 8)
12 of 25 april 9, 2001 IDT79RC32134 reset reset_boot_mode[1:0] i/o mem_addr[22:21] reset initialization vector used as reset initialization. vector input pins that are latched by coldreset_n de-asserting. reset_pci_host_mode i/o mem_addr[20] reset pci host mode used as reset initialization. vector input pins that are latched by coldreset_n de-asserting. program- ming for this signal is as indicated below: jtag jtag_tck i not applicable jtag test clock provides clock for boundary scan test cells. note: must be either dynamically driven or an external pull-up or pull-down resistor is required, if jtag is not being used. jtag_tms i not applicable jtag test mode this signal provides command/mode input for boundary scan test cells. an external pull-up resistor is required. jtag_tdi i not applicable jtag test data input provides data input for boundary scan test cells. an external pull-up resistor is required. jtag_tdo o not applicable jtag test data out provides data output for boundary scan test cells. jtag_trst_n i not applicable jtag test reset negated this active-low signal provides reset to boundary scan test cells. note: an external pull-up resistor is required. this pin must be driven low to reset the jtag tap controller, or held low if jtag is not being used. pin name type alternate signal(s) description table 2 rc32134 pin descriptions (page 8 of 8) value description 11 non-boot mode . idle at reset. this rc32134 does not supply boot code control. 10 reserved. 01 pci-boot mode. (pci_host_mode must be in satellite mode). rc32134 will reset either from a cold reset or from a pci reset. boot code is provided via pci. 00 standard-boot mode. boot from this rc32134?s memory controller (typical system). value description 1 pci is in satellite mode. 0 pci is in host mode (typical system).
13 of 25 april 9, 2001 IDT79RC32134 logic diagram ? rc32134 logic diagram ? rc32134 logic diagram ? rc32134 logic diagram ? rc32134 note: the alternate signals are listed in ?rc32134 alternate signal functions? on page 22 rc32134 logic symbol cpu_[31:0] cpu_addr[3:2] cpu_ale cpu_cip_n edodram_addr[15:2] edodram_ras_n[3:0] edodram_cas_n[3:0] cpu_wr_n cpu_be_n[3:0] cpu_ack_n mem_addr[2:2] mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] jtag_tck jtag_tms jtag_tdi v cc to io gnd mem_wait_n mem_245_oe_n jtag_tdo jtag_trst_n cpu_last_n cpu_buserr_n cpu_masterclk cpu_coldreset_n cpu_reset_n local memory / bus interface v cc io gnd memory & i/o bus jtag power / ground cpu_busreq_n cpu_busgnt_n cpu_int_n[3] cpu_dt_r_n mem_245_dt_r_n edodram / sdram edodram_oe_n edodram_we_n edodram_wait_n edodram_245_oe_n edodram_245_dt_r_n sdram_addr[15:13] sdram_ras_n sdram_cas_n sdram_we_n sdram_clk controller timer_tc_n[1:0] uart_rx[1:0] uart_tx[1:0] reset_boot_mode reset_pci_host_mode reset interrupt_n interrupt interface pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[2] pci_req_n[1] pci_req_n[0] pci_gnt_n[2] pci_gnt_n[1] pci_gnt_n[0] interface pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_cs pci_eeprom_mdo pci_eeprom_sk dma_ready_n[1:0] pio[11:0] pci interface controllers mem_addr[22:2] local memory sdram_cke sdram_cs[3:0] sdram_bemask_n[3:0] sdram_addr_12 sdram_245_oe_n dma interface pio timer uart interface /bus interface v cc to core v cc core sdram_245_dt_r_n sdram_addr[11:2]
14 of 25 april 9, 2001 IDT79RC32134 clock parameters ? rc32134 clock parameters ? rc32134 clock parameters ? rc32134 clock parameters ? rc32134 (tc = 0 c to +90 c commercial, tc = -40 c to +90 c industrial, v cc core = +3.3v 5%) figure 2 mode configuration interface reset sequence there is no special requirement for how fast vcc ramps up to 3.3v. however, all timing references are based on vcc stabilized a t 3.3v + 5%. parameter symbol test conditions rc32134 75mhz units min max cpu_masterclock high t mchigh transition 3ns 6 ? ns cpu_masterclock low t mclow transition 3ns 6 ? ns cpu_masterclock period t mcp 13.33 ? ns cpu_masterclock rise& fall time t mcrise, t mcfall ?3 ns pci_clk period t pcp 30 ? ns pci_clk rise& fall time t pcrise, t pcfall pci 2.1 ? 3 ns jtag_tck rise& fall time t jcrise, t jcfall ?5 ns jtag clock period jtag_clk 100 ? ns vcc cpu_coldreset_n modebit[9:0] cpu_reset*(internal >= 150 ms cpu_masterclk >= 10 ms (mclk) >= 64 mclk cycles signal)
15 of 25 april 9, 2001 IDT79RC32134 ac timing characteristics ? rc32134 ac timing characteristics ? rc32134 ac timing characteristics ? rc32134 ac timing characteristics ? rc32134 (tc = 0 c to +90 c commercial, tc = -40 c to +90 c industrial, v cc core = +3.3v 5%) signal symbol reference edge 75mhz unit user manual timing diagram reference min max local memory/ peripheral bus cpu_ad[31:0] (address phase), cpu_addr[3:2] tsu1 cpu_ale falling 3 ? ns chapter 3, figure 3.6 figure 3.7 figure 3.8 figure 3.9 figure 5.4 figure 8.8 figure 8.9 cpu_ad[31:0] (address phase), cpu_addr[3:2] thld1 cpu_ale falling 3 ? ns cpu_ad[31:0] (data phase) tsu2 cpu_masterclk rising 5.5 ? ns cpu_ad[31:0] (data phase) thld2 cpu_masterclk rising 0.7 ? ns cpu_ale rising tsu3 cpu_masterclk falling 0 ? ns cpu_ale falling (ale pulse width) tale high cpu_ale rising 4 ? ns cpu_busgnt_n, cpu_wr_n, cpu_be_n[3:0], cpu_last_n tsu4 cpu_masterclk rising 5 ? ns cpu_busgnt_n, cpu_wr_n, cpu_be_n[3:0], cpu_reset_n, cpu_last_n thld4 cpu_masterclk rising 0.7 ? ns cpu_cip_n tsu5 cpu_masterclk rising 5 ? ns cpu_cip_n thld5 cpu_masterclk rising 0.7 ? ns cpu_ack_n, cpu_buserr_n, cpu_reset_n tdo1 cpu_masterclk rising ? 8 ns cpu_busreq_n, cpu_int_n tdo2 cpu_masterclk rising ? 8 ns cpu_dt_r_n tdo3 cpu_masterclk rising ? 8 ns cpu_ad[31:0] tdo4 cpu_masterclk rising ? 8 ns cpu_ad[31:0] output hold time tdoh1 cpu_masterclk rising 1 1 ?ns cpu_ack_n, cpu_buserr_n, cpu_reset_n, cpu_busreq_n, cpu_int_n tdoh2 cpu_masterclk rising 0.5 ? ns dma dma_ready_n[1:0], dma_done_n[1:0] tsu7 cpu_masterclk rising 3 ? ns chapter 9, figures 9.6 & 9.7 dma_ready_n[1:0], dma_done_n[1:0] thld9 cpu_masterclk rising 0.5 ? ns memory-i/o controller mem_wait_n tsu6 cpu_masterclk rising 3 ? ns chapter 3, figure 3.6 figure 3.7 figure 3.8 mem_wait_n thld8 cpu_masterclk rising 0.5 ? ns mem_addr[22:2] tdo5 cpu_masterclk rising ? 8 ns mem_cs_n[5:0] tdo6 cpu_masterclk rising ? 8 ns mem_oe_n, mem_we_[3:0], mem_245_dt_r_n, mem_245_oe_n tdo7 cpu_masterclk rising ? 8 ns mem_addr[22:2] mem_cs_n[5:0] mem_oe_n, mem_we_[3:0], mem_245_dt_r_n, mem_245_oe_n tdoh3 cpu_masterclk rising 0.5 ? ns
16 of 25 april 9, 2001 IDT79RC32134 pci pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_idse, pci_perr_n, pci_serr_n, pci_rst_n, pci_devsel_n, pci_lock_n t_su pci_clk rising 7 ? ns note: refer to pci specification, revision 2.1 for a detailed timing diagram. pci_gnt_n[0] t_su(ptp) 10 ? ns pci_req_n[2:0] t_su(ptp) 12 ? ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_idse, pci_perr_n, pci_serr_n, pci_rst_n, pci_devsel_n, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_lock_n t_h pci_clk rising 0 ? ns pci_eeprom_mdi tsu pci_clk rising, pci_eeprom_sk falling 10 ns pci_eeprom_mdi thld pci_clk rising, pci_eeprom_sk falling 10 ns pci_eeprom_mdo, pci-eeprom_cs tp pci_clk rising, pci_eeprom_sk falling 10 ns pci_eeprom_sk tp pci_clk rising 12 ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_inta_n, pci_lock_n t_val pci_clk rising 2 11 ns pci_req_n[0], pci_gnt_n[2:0] t_val(ptp) pci_clk rising 2 12 ns sdram controller sdram_245_dt_r_n, sdram_addr[15:2] tdo8 cpu_masterclk rising ? 8 ns chapter 4, figure 4.4 sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_bemask_n[3:0] sdram_cke tdo9 cpu_masterclk rising ? 8 ns sdram_addr_12 tdo10 cpu_masterclk rising ? 8 ns sdram_245_oe_n tdo11 cpu_masterclk rising ? 8 ns sdram_245_dt_r_n, sdram_addr[15:2] tdoh4 cpu_masterclk rising 1 1 ?ns sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_bemask_n[3:0] sdram_cke sdram_addr_12 sdram_245_oe_n tdoh4 cpu_masterclk rising 1 1 ?ns edoddram controller edodram_wait_n tsu7 cpu_masterclk rising 3 ? ns chapter 5, figure 5.3 edodram_wait_n thld8 cpu_masterclk rising 0.5 ? ns edodram_addr[15:2], edodram_245_dt_r_n tdo12 cpu_masterclk rising ? 8 ns edodram_ras_n[3:0], edodram_cas_n[3:0], edodram_we_n, edodram_oe_n tdo13 cpu_masterclk rising ? 8 ns edodram_245_oe_n tdo14 cpu_masterclk rising ? 8 ns signal symbol reference edge 75mhz unit user manual timing diagram reference min max
17 of 25 april 9, 2001 IDT79RC32134 note: tsu x = input setup time to rc32134 thld x = input hold time to rc32134 tdo x = output propagation time from rc32134 tdoh x = output hold time from rc32134 edodram_addr[15:2], edodram_245_dt_r_n edodram_ras_n[3:0], edodram_cas_n[3:0], edodram_we_n, edodram_oe_n edodram_245_oe_n tdoh5 cpu_masterclk rising 1 1 ?ns chapter 5, figure 5.3 (continued) timer timer_tc_n[1:0], timer_gate_n[1:0] tsu8 cpu_masterclk rising 3 ? ns chapter 10, figures 10.6 and 10.7 timer_tc_n[1:0], timer_gate_n[1:0] thld10 cpu_masterclk rising 0.5 ? ns timer_tc_n[1:0], timer_gate_n[1:0] tdo15 cpu_masterclk rising ? 8 ns timer_tc_n[1:0], timer_gate_n[1:0] tdoh6 cpu_masterclk rising 1 1 ?ns pio pio[11:0] tsu7 cpu_masterclk rising 3 ? ns chapter 9, figures 9.6 and 9.7 pio[11:0] thld9 cpu_masterclk rising 0.5 ? ns pio[11], pio[9:0] tdo16 cpu_masterclk rising ? 10 ns pio[10] tdo19 cpu_masterclk rising ? 12 ns pio[11], pio[9:0] tdoh7 cpu_masterclk rising 1 1 ?ns pio[10] tdoh7 cpu_masterclk rising 1 1 ?ns uarts uart_rx[1:0], uart_tx[1:0] tsu9 cpu_masterclk rising 10 ns chapter 11, figure 11.15 uart_rx[1:0], uart_tx[1:0] thld11 cpu_masterclk rising 10 ns uart_rx[1:0], uart_tx[1:0] tdo16 cpu_masterclk rising ? 10 ns uart_rx[1:0], uart_tx[1:0] tdoh8 cpu_masterclk rising 1 1 ?ns interrupt handling interrupt_n tdo2 cpu_masterclk rising ? 8 ns chapter 8, figures 8.8 and 8.9 interrupt_n tdoh2 cpu_masterclk-rising 1 1 ?ns reset reset_boot_mode, reset_pci_host_mode tsu8 cpu_masterclk-rising 3 ns chapter 2, figure 2.6 reset_boot_mode, reset_pci_host_mode thld12 cpu_masterclk-rising 0.5 ns jtag interface jtag_tms, jtag_tdi, jtag_trst_n tsu jtag_tck rising 10 ns refer to figure 2 below jtag_tms, jtag_tdi, jtag_trst_n thld jtag_tck rising 10 ns jtag_tdo tdo18 jtag_tck falling ? 10 ns signal symbol reference edge 75mhz unit user manual timing diagram reference min max
18 of 25 april 9, 2001 IDT79RC32134 figure 3 standard jtag timing o o o output loading for ac testing (for non-pci signals) utput loading for ac testing (for non-pci signals) utput loading for ac testing (for non-pci signals) utput loading for ac testing (for non-pci signals) note: pci pins have been correlated to pci 2.1. recommended operation temperature and supply voltage recommended operation temperature and supply voltage recommended operation temperature and supply voltage recommended operation temperature and supply voltage c c c capacitive load deration apacitive load deration apacitive load deration apacitive load deration refer to the idt document ?rc32134 ibis model? under sub-category rc32134 integrated processor on the company?s web page for pr ocessors (http://www.idt.com/products/pages/processors.html) . signal cld all signals 50 pf grade temperature gnd v cc io v cc core commercial 0 c to +90 c (case) 0v 3.3v5% 3.3v5% industrial -40 + 90 c (case) 0v 3.3v5% 3.3v5% jtag_tdi/ jtag_tms jtag_tdo jtag_ trst jtag_tck t3 t1 t2 t su t hld t do t4 t tck notes to diagram: t1 = t tcklow t2 = t tckhigh t4 = t rst (reset pulse width) t3 = t tckfall > = 25 ns t5 t5 = t tckrise ? + to device under test c ld v ref +1.5v
19 of 25 april 9, 2001 IDT79RC32134 d d d dc electrical characteristics c electrical characteristics c electrical characteristics c electrical characteristics tc = 0 c to +90 c commercial, tc = -40 c to +90 c industrial, v cc core = +3.3v 5% power consumption?rc32134 power consumption?rc32134 power consumption?rc32134 power consumption?rc32134 parameter rc32134 75mhz pin numbers conditions minimum maximum low drive pads v ol ? 0.4v 1, 2, 3, 4, 5, 8, 15, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 104, 106, 118, 133, 137, 142, 161 |i out | = 10.8ma v oh v cc - 0.4v ? |i out | = 7.8ma v il ?0.8v ? v ih 2.0v v cc + 2.0v high drive pads v ol ? 0.4v 9, 10, 11, 12, 13, 107, 108, 109, 112, 113, 114, 115, 116, 117, 119, 122, 123, 124, 125, 126, 129, 132, 134, 135, 138, 139, 143, 144, 146, 147, 149, 152, 154, 155, 159, 160, 165, 167, 168, 169, 170, 171, 174, 175, 176, 177, 178, 179, 180, 181, 184, 185, 186, 187, 188, 189, 190, 191, 194, 195, 196, 197, 198, 199, 200, 201, 204, 205, 206, 207, 208 |i out | = 19ma v oh v cc - 0.4v ? |i out | = 15.6ma v il ?0.8v ? v ih 2.0v v cc + 2.0v pci drive pads v ol ? 0.4v 35, 39, 42, 43, 45, 48, 49, 50, 51, 52, 53, 54, 55, 56, 60, 61, 62, 63, 64, 65, 66, 67, 70, 71, 72, 73, 74, 75, 77, 80, 81, 82, 83, 84, 85, 86, 87, 90, 91, 92, 93, 94, 95, 96, 97, 100, 101, 102, 103 |i out | = 25ma v oh v cc - 0.4v ? |i out | = 19.5ma v il ?0.8v v ih 2.0v 5.5 ? c in ? 10pf all except 41, 57 ? c in 5pf 12pf 41 per pci 2.1 c in 8pf 57 per pci 2.1 c out ? 10pf all output pads ? i/o leak ? 20ua all pins input/output leak- age parameter rc32134 75mhz conditions typical l cc p typ 360ma 1.2w c l = 50pf ta= 25 o c v cc core = 3.3v v cc io = 3.3v cpu_masterclk = 75mhz pci_clk = 33mhz max l cc p max 460ma 1.6w c l = 50pf ta= 55 o c v cc core = v cc core max v cc io = 3.47v cpu_masterclk = 75mhz pci_clk = 33mhz
20 of 25 april 9, 2001 IDT79RC32134 absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. package pin-out - 208-pqfp package pin-out - 208-pqfp package pin-out - 208-pqfp package pin-out - 208-pqfp the following table lists the pin numbers and signal names for the rc32134. to maximize pin usage, several pins have alternate functions, as noted in the ?alt? column and described in ?rc32134 alternate signal functions? on page 22. signal names ending with an _n are active when low. symbol parameter min max unit v cc supply voltage -0.3 4.0 v vi input voltage gnd 5.5 v tstg storage temperature -40 125 degrees c ta ambient temperature value 0 70 degrees c pin function alt pin function alt pin function alt pin function alt 1 mem_cs_n[5] 53 pci_ad[26] 105 cpu_wr_n 157 cpu_coldreset_n 2 mem_cs_n[4] 54 pci_ad[25] 106 cpu_reset_n 158 cpu_be_n[3] 3 mem_cs_n[3] 55 pci_ad[24] 107 cpu_ad[21] 159 cpu_ad[20] 4 mem_cs_n[2] 56 pci_cbe_n[3] 108 cpu_ad[9] 160 cpu_ad[11] 5 mem_cs_n[1] 57 pci_req_n[2] (host mode) 1 109 cpu_ad[22] 161 cpu_busreq_n 6 vcc i/o 58 v cc i/o 110 v cc i/o 162 v cc i/o 7v ss 59 v ss 111 v ss 163 v ss 8 mem_cs_n[0] 60 pci_ad[23] 112 cpu_ad[8] 164 cpu_addr[2] 9 mem_oe_n 61 pci_ad[22] 113 cpu_ad[23] 165 cpu_ad[10] 10 mem_we_n[3] 62 pci_ad[21] 114 cpu_ad[7] 166 cpu_addr[3] 11 mem_we_n[2] 63 pci_ad[20] 115 cpu_ad[24] 167 mem_addr[22] 1 12 mem_we_n[1] 64 pci_ad[19] 116 cpu_ad[6] 168 mem_addr[21] 1 13 mem_we_n[0] 65 pci_ad[18] 117 cpu_ad[25] 169 mem_addr[20] 1 14 mem_wait_n 2 66 pci_ad[17] 118 cpu_dt_r_n 3 170 mem_addr[19] 15 mem_245_oe_n 67 pci_ad[16] 119 cpu_ad[5] 171 mem_addr[18] 16 v cc i/o 68 v cc i/o 120 v cc i/o 172 v cc i/o 17 v ss 69 v ss 121 v ss 173 v ss 18 dma_ready_n[1] 2 70 pci_cbe_n[2] 122 cpu_ad[26] 174 mem_addr[17] 19 dma_ready_n[0] 2 71 pci_frame_n 123 cpu_ad[4] 175 mem_addr[16] 20 timer_tc_n[1] 2 72 pci_irdy_n 124 cpu_ad[27] 176 mem_addr[15] 2 21 timer_tc_n[0] 2 73 pci_trdy_n 125 cpu_ad[3] 177 mem_addr[14] 2 table 3: rc32134 208-pin qfp package pin-out (page 1 of 2)
21 of 25 april 9, 2001 IDT79RC32134 22 uart_rx[1] 1 74 pci_devsel_n 126 cpu_ad[28] 178 mem_addr[13] 2 23 uart_tx[1] 1 75 pci_stop_n 127 cpu_cip_n 179 sdram_bemask_n[3] 1 24 uart_rx[0] 1 76 pci_lock_n 128 cpu_last_n 180 sdram_bemask_n[2] 1 25 uart_tx[0] 1 77 pci_perr_n 129 cpu_ad[2] 181 sdram_cs_n[3] 1 26 v cc core 78 v cc core 130 v cc core 182 v cc core 27 v ss 79 v ss 131 v ss 183 v ss 28 pci_eeprom_mdo 1 80 pci_serr_n 132 cpu_ad[29] 184 sdram_cs_n[2] 1 29 pci_eeprom_mdi 1 81 pci_par 133 cpu_buserr_n 185 sdram_cke 30 pci_eeprom_sk 1 82 pci_cbe_n[1] 134 cpu_ad[1] 186 mem_addr[12] 1 31 sdram_addr_12 1 83 pci_ad[15] 135 cpu_ad[30] 187 mem_addr[11] 2 32 jtag_trst_n 84 pci_ad[14] 136 cpu_ale 188 mem_addr[10] 2 33 jtag_tck 85 pci_ad[13] 137 cpu_ack_n 189 mem_addr[9] 2 34 jtag_tms 86 pci_ad[12] 138 cpu_ad[0] 190 mem_addr[8] 2 35 jtag_tdo 87 pci_ad[11] 139 cpu_ad[31] 191 mem_addr[7] 2 36 v cc i/o 88 v cc i/o 140 v cc i/o 192 v cc i/o 37 v ss 89 v ss 141 v ss 193 v ss 38 jtag_tdi 90 pci_ad[10] 142 cpu_masterclk 1 194 mem_addr[6] 2 39 pci_gnt_n[2] (host mode) 1 91 pci_ad[9] 143 cpu_ad[15] 195 mem_addr[5] 2 40 pci_rst_n 92 pci_ad[8] 144 cpu_ad[16] 196 mem_addr[4] 2 41 pci_clk 93 pci_cbe_n[0] 145 cpu_be_n[0] 197 mem_addr[3] 2 42 pci_gnt_n[1] (host mode) 1 94 pci_ad[7] 146 cpu_ad[17] 198 mem_addr[2] 2 43 pci_gnt_n[0] 95 pci_ad[6] 147 cpu_ad[14] 199 sdram_ras_n 1 44 pci_req_n[1] (host mode) 1 96 pci_ad[5] 148 cpu_be_n[1] 200 sdram_cs_n[1] 1 45 pci_req_n[0] 97 pci_ad[4] 149 cpu_ad[18] 201 sdram_cs_n[0] 1 46 v cc i/o 98 v cc i/o 150 v cc i/o 202 v cc i/o 47 v ss 99 v ss 151 v ss 203 v ss 48 pci_ad[31] 100 pci_ad[3] 152 cpu_ad[13] 204 sdram_bemask_n[1] 1 49 pci_ad[30] 101 pci_ad[2] 153 cpu_be_n[2] 205 sdram_bemask_n[0] 1 50 pci_ad[29] 102 pci_ad[1] 154 cpu_ad[19] 206 sdram_cas_n 51 pci_ad[28] 103 pci_ad[0] 155 cpu_ad[12] 207 sdram_we_n 1 52 pci_ad[27] 104 cpu_int_n[3] 1 156 cpu_busgnt_n 208 sdram_245_oe_n 2 pin function alt pin function alt pin function alt pin function alt table 3: rc32134 208-pin qfp package pin-out (page 2 of 2)
22 of 25 april 9, 2001 IDT79RC32134 rc32134 alternate signal functions rc32134 alternate signal functions rc32134 alternate signal functions rc32134 alternate signal functions pin alt #1 alt #2 alt #3 pin alt #1 alt #2 alt #3 14 sdram_wait_n edodram_wait_n na 169 reset_pci_host_mode na na 18 dma_done_n[1] pio[0] na 179 edodram_cas_n[3] na na 19 dma_done_n[0] pio[1] na 180 edodram_cas_n[2] na na 20 timer_gate_n[1] pio[2] na 181 edodram_ras_n[3] na na 21 timer_gate_n[0] pio[3] na 184 edodram_ras_n[2] na na 22 pio[5] na na 186 edodram_addr[12] na na 23 pio[4] na na 187 sdram_addr[11] edodram_addr[11] na 24 pio[7] na na 188 sdram_addr[10] edodram_addr[10] na 25 pio[6] na na 189 sdram_addr[9] edodram_addr[9] na 28 pio[11] na na 190 sdram_addr[8] edodram_addr[8] na 29 pio[8] na na 191 sdram_addr[7] edodram_addr[7] na 30 pio[10] na na 194 sdram_addr[6] edodram_addr[6] na 31 pio[9] na na 195 sdram_addr[5] edodram_addr[5] na 39 pci_inta_n satellite na na 196 sdram_addr[4] edodram_addr[4] na 42 na pci_eeprom_cs (satellite ) na 197 sdram_addr[3] edodram_addr[3] na 44 unused (satellite) na na 198 sdram_addr[2] edodram_addr[2] na 57 pci_idsel (satellite) na na 199 edodram_oe_n na na 104 interrrupt_n na na 200 edodram_ras_n[1] na na 118 mem_245_dt_r_n sdram_245_dt_r_n edodram_245_dt_r_n 201 edodram_ras_n[0] na na 142 sdram_clk na 207 edodram_we_n na na 167 reset_boot_mode[1] na 208 edodram_245_oe_n edodram_oe_n na 168 reset_boot_mode[0] na
23 of 25 april 9, 2001 IDT79RC32134 package drawing - 208-pin pqfp package drawing - 208-pin pqfp package drawing - 208-pin pqfp package drawing - 208-pin pqfp
24 of 25 april 9, 2001 IDT79RC32134 package drawing - page two package drawing - page two package drawing - page two package drawing - page two
25 of 25 april 9, 2001 IDT79RC32134 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408- 330-1748 www.idt.com for tech support: email: rischelp@idt.com phone: 408-492-8208 the idt logo is a registered trademark of integrated device technology, inc. ordering information ordering informationordering information ordering information valid combinations valid combinationsvalid combinations valid combinations idt79rc32v134 ds 208-pin pqfp package - commercial temperature idt79rc32v134 dsi 208-pin pqfp package - industrial temperature idt79rcxx v ddd pp t operating voltage device type package temp range/ process 32134 ds = blank = commercial temperature (0c to +90c case) 208-pin pqfp v = 3.3v 5% system controller i = industrial temperature (-40c to +90c case) product type idt79rc32 = 32-bit family product 134 =

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